Exploiting Arithmetic Built-In-Self-Test Techniques for Path Delay Fault Testing

This thesis describes the implementation of a system for analyzing circuits with respect to their path-delay fault testability. The system includes a path-delay fault simulator and an ATPG for path-delay faults combined into a test tool. This test tool can run standalone on a single machine, or as one of several clients that communicate through a central server. The test tool is used in this thesis in order to evaluate the performance of 14 different test vector generators that can be used in various built-in self-test arrangements. The test generators exploit pseudo-random stimuli generation. We have used six different strategies for weighting of input signals, and performed comprehensive experiments to evaluate the efficiency of the strategies. Each of the experiments typically consists of three phases: • In the first phase, the ATPG is used in order to find the K-longest nonrobust testable path-delay faults. The corresponding path numbers are then saved together with the corresponding test vector for later use. The paths constitute the target fault list during simulation. Experiments that consider all possible faults skip this phase. • In the second phase, weights are generated for the weighted pseudorandom generators. These weights are stored for later use. This phase is skipped for experiments where the generator is unweighted. • In the third phase the actual simulation takes place. In all experiments 10M single-input-change test patterns were applied and repeated ten times for each generator and circuit in order to cover some statistical variations. Only non-robust faults (including robust faults) were considered. Two groups of pseudo-random generators have been evaluated. The first group, GA, consists of accumulator based pseudo-random generators. The second group, GT, consists of Mersenne twister based pseudo-random generators.